The present invention relates to semiconductor devices, and more particularly to semiconductor devices utilizing vertical transistors.
The semiconductor industry is constantly trying to decrease the size of semiconductor devices. The need for miniaturization is needed in order to accommodate the increasing density of circuits necessary for today's semiconductor products. It is not uncommon for a single semiconductor product to include, for example, over a million semiconductor devices.
Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device. Device sizes have approached sizes down to 0.2 microns and less. However, the decrease in the horizontal dimensions of semiconductor devices have created problems in the operational characteristics of the semiconductor devices.
FIG. 1 is a cross-sectional view of a prior art semiconductor device, representing, for example, a dynamic random access memory (DRAM) device. Referring to FIG. 1, semiconductor device 100 is typically comprised of several layers. The semiconductor device begins with a silicon substrate 103 upon which the other elements of the semiconductor device are built. In the illustrated example of a prior art semiconductor device, semiconductor device 100 is a dual device containing two separate semiconductor devices 100a and 100b.
Within the substrate, deep trenches 112 are created with polysilicon. Surrounding the deep trenches are dielectric layers 140. Dielectric layers 140 are typically comprised of a thick dielectric to insulate deep trenches 112. Additionally, the deep trenches of separate devices are isolated by silicon barriers 142 that are typically extensions of substrate 103. Between deep trenches 112 is an active area 145. Active area 145 is primarily composed of silicon.
Above silicon barriers 142 are shallow trench isolation layers 149. Shallow trench isolation layers 149 are typically composed of a thin dielectric. The shallow trench layers typically provide further isolation between two adjacent semiconductor devices 100.
Within active area 145 doped regions 151, 152 and 153 are typically formed to create the active components of the semiconductor device. Doped regions 151, 152 and 153 may be doped n or p type depending upon the type of device desired.
Connected to doped region 153 is a bit line contact 118 that electrically couples doped region 153 to bit line 130. Immediately above doped regions 151 and 152 is an oxide layer 156 that isolates doped regions 151 and 152. Adjacent to doped regions 151 and 152, and above oxide layer 156, are word lines 120. A depletion region 160 is created in active area 145 between doped regions 152 and 153 by properly biasing word line 120a with respect to substrate 103 and bit line 130. When word line 120a is further biased, an inversion region 161 is created within active area 145. Inversion layer 161 allows a current to flow between doped region 153 and deep trench 112. The direction of the current depends upon the bias of bit line 130 with respect to substrate 103.
Typically, current flows between bit line 130 and deep trench 112 through bit line contact 118, doped region 153 and inversion region 161 to deep trench 112. Depending upon the bias of bit line 130 charge can be stored within deep trench 112 or discharged from deep trench 112. Dielectric layers 140 act as insulators to preserve the charge stored in deep trench 112.
Thus, word lines 120 act as a gate for semiconductor devices 100a and 100b. Bit line 130 is the drain or source, depending upon the biasing of the device; and deep trench 112 is the source or drain.
FIG. 2 is a top perspective view of several prior art semiconductor devices 100 of FIG. 1. The cross-sectional view of FIG. 1 is taken along lines 1--1. The different layers of the semiconductor devices are depicted in FIG. 2. The size of a single device (e.g., 100a or 100b) is measured by device area 180. The size of prior art semiconductor devices typically approach 8F.sup.2, where F is the minimum device size, or dimension capable by the fabrication process (e.g., 0.2 microns). Even with further miniaturization in the horizontal plane smaller device areas are difficult to achieve.
The smaller the device area of a semiconductor device, more problems develop in the operation of the semiconductor device. For example, hot carriers and punch through problems occur in devices of small dimensions resulting, e.g., in a degraded gate oxide which typically destroys the semiconductor device.
Due to these types of problems, the small planar scale semiconductor devices must be operated in exacting conditions. Thus, more circuitry is required to operate the devices.
Further, small errors in fabrication of the small scale planar semiconductor devices have greater detrimental effects on the semiconductor devices. For example, if word line 120, which is the gate, is located too close or over the deep trench 112, the device would not operate properly due to leakage currents.
One method of trying to miniaturize semiconductor devices without having to significantly reduce the actual size of the device is to create vertical devices. FIG. 3 depicts a prior art vertical transistor device 300. The vertical transistor 300 minimizes the device area while at the same time allowing the semiconductor size to be of a manageable size for purposes of operation. Vertical semiconductor device 300 operates similar to planar semiconductor device 100.
Vertical semiconductor device 300 includes a bit line contact 318, a doped region 353, a word line 320 and a deep trench 312. Bit line contact 8 is coupled to a bit line (not shown). Word line 320 acts as a gate, and creates a depletion region 360 when properly biased. When word line 320 is further biased to create an inversion region 361 a current flows from the bit line through bit line contact 318 to deep trench 312, or vice versa.
While prior art vertical semiconductor devices provide small area sizes and device sizes that are not detrimentally small, prior art vertical semiconductor devices prevent further fabrication of devices over the vertical semiconductor devices due to their topography. For example, in FIG. 3, the topography of the device above deep trench 312 is irregular due to the irregular formation of word line 320. Thus, further layers placed over the irregular topography typically form irregularly. In CMOS processing further fabrication of devices requires a substrate layer free of topographical irregularities. Thus, in CMOS processes, further fabrication is hampered over the prior art semiconductor device due to the irregular topography.
Additionally, logic circuits are typically formed on a circuit region 370 on the same substrate as the prior art vertical semiconductor device. Typically, the vertical device, in this case a dynamic random access memory (DRAM) device, is formed first on the substrate. In further steps circuit region 370 is formed. The separate processing steps causes differences in elevation between the prior art vertical semiconductor device and circuit region 370. Word line 320 is significantly offset from any subsequent word lines formed on circuit region 370. Also, due to the irregular topographies of word lines 320 of prior art vertical semiconductor device 300 the circuit region 370 are at a different elevation than any subsequent logic circuits that may be applied over the prior art vertical semiconductor device. Thus, intercoupling of the logic circuits formed on circuit region 370 and subsequent logic circuits that may be formed over prior art vertical semiconductor device 300 is further hampered because of the elevational differences.
In view of the foregoing, there are desired improved methods and apparatus for overcoming the disadvantages associated with prior art semiconductor devices. More particularly, a semiconductor device that minimizes device area sizes, while not overly minimizing device sizes and not limiting further device fabrication and methods for making same is desired.